Virtual Boy - Sacred Tech Scroll

Overview
Memory Map
ROM Format
System Reset
About
Change Colors

System Components
CPU - NVC/V810 Family Microprocessor
Communication Port
Game Pad
Game Pak
Timer
Wait Controller
VIP - Virtual Image Processor
VSU - Virtual Sound Unit

Memory Map

The Virtual Boy memory bus is 27 bits wide and is organized by hardware component:

The upper 5 bits of any address in the 0x08000000 - 0xFFFFFFFF range are masked, making the maximum effective address 0x07FFFFFF and producing mirrors of the contents of memory across the entire address range.

Writes to the unmapped address range 0x03000000 - 0x03FFFFFF have no effect, and reads in that range will return zero.

WRAM is 64 KiB in size: its effective address range is 0x05000000 - 0x0500FFFF. Any addresses in the 0x05010000 - 0x05FFFFFF range consequently have bits 16-23 masked, producing mirrors of the contents of WRAM across the entire address range.

For information on the Game Pak Expansion, Game Pak RAM and Game Pak ROM address ranges, see Game Pak.

WRAM

WRAM is pseudostatic RAM that has specific initialization requirements:

Virtual Boy software must account for this initialization before accessing WRAM, or else its behavior is undefined.

Miscellaneous Hardware

Registers for various hardware components occupy addresses 0x02000000 - 0x02FFFFFF in the system memory map:

Hardware I/O registers are intended to be accessed as bytes. However, the registers are spaced 4 bytes apart, so any type of access can be used with them.

Writing to unmapped addresses has no apparent effect, and all bits in any byte not listed above will be undefined when read.

ROM Format

Memory addresses 0xFFFFFDE0 - 0xFFFFFFF must contain specific kinds of data. Due to the address mirroring behavior of the memory map, these addresses correspond with addresses 0x07FFFDE0 - 0x07FFFFFF in the game pak ROM address range. The significance of these addresses is described below.

Due to the address mirroring behavior of the game pak ROM address range in all commercial game paks, addresses starting at 0x07FFFDE0 are traditionally located at the end of the ROM data, regardless of the size of the ROM module.

ROM Header

Memory addresses 0xFFFFFDE0 - 0xFFFFFDFF contain the ROM header:

Nintendo maintains a list of maker codes that is beyond the scope of this document.

The game codes for commercial software are printed on the packaging and game pak labels.

Exception Handlers

Memory addresses 0xFFFFFE00 - 0xFFFFFFFF contain the CPU exception handlers:

The data at these addresses is CPU instructions for processing the exceptions. At 16 bytes each, there is enough room to construct an address and jump to it.

CPU - NVC/V810 Family Microprocessor

Overview
Specifications
Data Types
Register Set
Instruction Cache
Instruction Formats

Exceptions
Exceptions
Exception Processing
List of Exceptions

Instruction Set
Memory and Register
Arithmetic
Bitwise
CPU Control
Floating-Point
Bit Strings
Miscellaneous
Nintendo

Appendix
Assembly Notation
Condition Numbers
Opcode Map
System Register Numbers

Specifications

Virtual Boy uses a modified NEC V810 CPU called NVC:

A handful of instructions were added by Nintendo, but otherwise the processor is the same as the stock V810.

The I/O bus is mapped to the memory bus: all read and write instructions access the same data.

Editor's Note: Three system registers are functional on NVC that are not mentioned in the V810 manual. It's possible Nintendo may have introduced them, but so far no record of where they came from can be found.

Data Types

Operations on NVC registers can take place on five different types of data:

All multi-byte data types are accessed in memory with the lowest-order byte at the lowest address within the data type (little-endian).

Memory accesses are aligned: the address being accessed is divisible by the number of bytes in the corresponding data type. If an unaligned access is attempted, the lowest-order bits of the address are ignored and the effective address is rounded down to the next lower multiple of the size in bytes of the data type.

Dedicated instructions exist for converting between word and floating short data types.

Register Set

All CPU registers are 32 bits wide.

Program Counter

The program counter (PC) stores the address of the current instruction being executed. After an instruction completes, the address in PC is updated in preparation of the next instruction. This is done automatically, although a branch or jump instruction specifies the new address directly.

If an instruction raises an exception, PC will generally not be changed. Accordingly, it is the responsibility of the exception handler to modify the corresponding "PC" status-saving register before returning in order to prevent the exception from immediately being raised again.

The lowest-order bit of PC is always clear: instructions always begin on a 16-bit boundary.

Program Registers

There are 32 general-purpose registers that can be used by programs for whatever reason, called program registers. Program registers are named r0 through r31 and they all behave the same way, with the exception of r0, which has a fixed value of zero.

While program registers can be used for whatever purpose by the program, specific registers are used by certain instructions as input or output targets. The following program registers have significance regarding the execution of CPU instructions:

Certain program registers have names according to their intended use by compilers and assemblers:

Calling Convention

Upon entering a function, the calling convention defines the following roles for program registers:

When a function completes, any return value will be stored in r10.

If more than four arguments are passed to a function, additional arguments will be located on the stack such that the fifth argument is pointed to by r3 + 16 and subsequent arguments follow at consecutively higher addresses. The callee is not responsible for cleaning up these arguments from the stack before returning: the value of r3 will remain the same when returning as it was upon entering the function.

The 16 bytes preceding the fifth argument on the stack are designated as spill space in the caller's stack frame and may be written by the callee.

Registers r1 and r6 through r31 are not guaranteed to be preserved during a function call.

Editor's Note: Is it correct that the spill area is in the caller's stack frame? Is it absent when fewer than five arguments are present?

System Registers

System registers are additional registers that can't be used by the program directly, but represent and configure CPU operating behavior. There are 13 system registers:

System registers can be accessed by the program through the LDSR and STSR instructions, which transfer values between system registers and program registers.

The format and functionality of each system register is described below.

ADTRE - Address Trap Register for Execution

Configures the execution address of the address trap, which is a hardware breakpoint feature.

CHCW - Cache Control Word

Configures the instruction cache. The significance of the bits varies depending on the context in which the register is used:

If CEN ≥ 128, no dump or restore operation will be performed.

If CEC > 128, the actual number of entries to clear becomes 128.

A clear operation will stop after it clears entry 127.

If more than one of ICR, ICD or ICC are specified simultaneously, the operation is undefined.

ECR - Exception Cause Register

Indicates the source of an exception:

This register cannot be modified by the LDSR instruction.

EIPC, EIPSW, FEPC, FEPSW - Status-saving registers

Whenever an exception occurs, the values of PC and PSW are copied into the corresponding status-saving registers prior to handling the exception:

EIPC and FEPC share the same format as PC: the lowest-order bit is always clear.

EIPSW and FEPSW share the same format as PSW: reserved bits in PSW likewise cannot be written in EIPSW or FEPSW.

PIR - Processor ID Register

Contains the identification code of the processor:

This register is read-only and contains a fixed value of 0x00005346.

Editor's Note: The NVC format of PIR differs slightly from the V810 format.

PSW - Program Status Word

Contains status flags and an interrupt masking level:

During the operation of the Bcond and SETF instructions, certain flag state combinations are checked in PSW.

TKCW - Task Control Word

Specifies how floating-point operations are to be processed:

This register is read-only and contains a fixed value of 0x000000E0. This corresponds to the following configuration:

Editor's Note: Since this register was never intended to be modifiable, the effects of other values for RDI and RD were not provided in the documentation for the V810 or V830 processors.

29 - System register 29

This register has unknown significance:

30 - System register 30

This register has unknown significance:

This register is read-only and contains a fixed value of 0x00000004.

31 - System register 31

Calculates the absolute value of a signed word:

Reading from this register will give the absolute value of the most recent value written to it.

Instruction Cache

NVC provides 1 KiB of CPU instruction cache. There are 128 cache entries with a block size of 8 bytes each for a total of 1,024 bytes of cache memory. The benefit of using the instruction cache is to accelerate the execution of program code. This is accomplished by storing program code directly on the CPU so that it doesn't need to be read from the memory bus every time it is needed.

The instruction cache is managed through the CHCW system regster. Cache entries can be cleared directly, and the full contents of the cache can be dumped to and restored from main memory.

Associated with each cache entry is a tag representing the upper 22 bits of the memory address of the corresponding data, and a bit specifying whether the entry contains valid cached data. These fields are used in conjunction with the block memory to represent the cached data.

When an instruction fetch read is performed, the address to be accessed is parsed in the following way:

The cache entry is selected by Index. If the entry does not contain valid data or if its tag does not match Tag, the corresponding data is read from memory and stored into the cache entry.

During dump and restore operations, both the block data and the tag data are written to/read from main memory. At the memory location specified by SA in CHCW, all 128 8-byte blocks are stored in order, followed by all 128 4-byte tags for a total of 1,536 bytes.

The format of the tag data dumped or restored for one cache entry is as follows:

Valid can be explicitly reset by performing a clear operation through CHCW. This will immediately free the cache entry and the next access whose Index matches will be loaded into cache memory.

Interrupts are postponed until the completion of dump and restore operations.

Instruction Formats

Instructions are fetched as halfword units from the bus and may be 16 or 32 bits in size. A common opcode field is present in the highest-order bits of the first halfword of every instruction, which is used to determine the instruction's binary format and whether an additional 16 bits need to be fetched.

If an instruction is 32 bits in size, a second halfword is fetched from the bus at the immediate next higher halfword address. The resulting word value is formed by taking the first halfword (bits 0-15) as the upper 16 bits and the second halfword (bits 16-31) as the lower 16 bits.

Every instruction is encoded into one of seven binary formats, referred to as Format I through Format VII. The structure of each of these instruction formats is described below.

Format I - Register-Register

16 bits. Used for register-to-register operations.

Format II - Immediate-Register

16 bits. Used for immediate-to-register operations.

Depending on the instruction, imm may or may not be sign-extended.

Format III - Conditional Branch

16 bits. Used by the Bcond instruction for short-distance branches.

For the numeric codes of each condition, see Bcond.

The displacement offset is measured in bytes relative to the address of the first byte of the instruction.

This is the only format that does not have a 6-bit opcode field. The 3 bits that represent the Bcond instruction's opcode (100) are not shared as the upper 3 bits of any other instruction's opcode.

Format IV - Middle-Distance Jump

32 bits. Used for middle-distance jumps using a displacement offset.

The displacement offset is measured in bytes relative to the address of the first byte of the instruction.

Format V - 3-Operand

32 bits. Used for operations that require three operands.

Depending on the instruction, imm may or may not be sign-extended.

Format VI - Load/Store

32 bits. Used for memory access operations.

The effective address of the memory access operation is determined by adding disp to the value in register reg1.

For load and input operations, register reg2 receives the value read. For store and output operations, it supplies the value to write.

Format VII - Extended

32 bits. Functions similarly to Format I, but with additional opcodes.

Exceptions

Certain events can cause the CPU to break its current execution, save its status and begin execution somewhere else according to what happened. The general term for such an occurrence is exception, and exceptions come in three froms:

Every exception has an associated 16-bit code and a 32-bit handler address. When an exception is raised, the code is stored into ECR and the handler address into PC. For a list of codes and handler addresses, see List of Exceptions.

Exception

Processing of CPU instructions can raise exceptions on their own. This can happen in the following situations:

Interrupt

Hardware components other than the CPU are allowed to request interrupts. This provides a mechanism to synchronize all system operations as well as a way for a hardware component to signal the program when certain conditions are met.

Interrupts can be disabled by setting the ID flag in PSW. The CLI and SEI instructions manipulate this flag directly, and the LDSR instruction can also be used to configure it.

Each hardware component that can request an interrupt is assigned a numeric level. Interrupts with greater levels are given priority over and are accepted before interrupts with lesser levels. If the interrupt's level is less than the value of the I field in PSW, the interrupt request will be ignored.

When an interrupt is requested, it will not be accepted until after the current CPU instruction or cache dump or restore operation has finished processing.

Interrupts are ignored during exception processing: when either of the EP or NP flags is set in PSW.

The HALT instruction will stop all CPU activity until an interrupt request is accepted, at which point it will resume with exception processing.

Address Trap

A hardware breakpoint can be configured to raise an exception when the CPU is about to execute an instruction at the configured address.

The ADTRE system register can be configured with the breakpoint address, and the address trap function can be enabled by setting the AE flag in PSW. Under these conditions, if the value of PC matches ADTRE prior to fetching the instruction at that address, an address trap exception will be raised.

Duplexed Exception

If an exception is raised during the processing of another exception, a duplexed exception occurs. The return status of both exceptions is held in ECR and the status-saving registers, and a special handler specifically for duplexed exceptions is run.

If an exception is raised during the processing of a duplexed exception, a fatal exception occurs. Debugging information is written to the memory bus and the CPU enters a permanent halt state until reset. For more information, see Exception Processing.

Exception Processing

Restore PC

When exception handling begins, the contents of PC and PSW are transferred into the appropriate status-saving registers. The value used for PC in this case is known as the restore PC, and is determined relative to the address of the current instruction being executed.

The following exceptions will use the address of the current instruction, known as current PC, as the restore PC:

The following exceptions will use the address of the following instruction, known as next PC, as the restore PC:

Interrupt Handling

An interrupt that is requested will only be accepted if all of the following conditions are met:

Exception Handling

When an exception is raised, the following algorithm is carried out:

Editor's Note: Research is needed to determine the number of cycles taken by this process.

Returning from Exceptions

When handling of an exception is completed, control is returned to the program with the RETI instruction.

According to the NP flag of PSW, RETI will restore PC and PSW from the appropriate status-saving registers.

List of Exceptions

This list is ordered such that items that appear earlier in the list have higher priority than items that appear later in the list. If any two exceptions should coincide, the one with the highest priority is the one that will be processed.

Although interrupts are given high priority, they cannot occur simultaneously with instruction exceptions because the CPU checks for interrupt requests in between executing instructions. Bit string instructions are not actually interrupted during processing, but rather they are executed repeatedly and only update PC once they fully complete.

The reset interrupt is automatically acknowledged when the CPU is initialized. PSW is initialized in such a way that the I field is zero, so reset has no meaningful interrupt level.

If a floating-point instruction satisfies multiple error conditions (such as dividing NaN by zero), only the one with the highest priority will be processed and have its status flag set in PSW.

Memory and Register

Register Transfer

The purpose of the MOVEA and MOVHI instructions is to provide a means for populating a register with 32 bits of immediate data without modifying the status flags in PSW.

Since MOVEA sign-extends its immediate value, care needs to be taken to ensure that the appropriate value is stored in the upper halfword of the register via MOVHI.

Load and Input

Halfword operations will mask the lowest bit of the effective address to 0, and word operations will mask the two lowest bits to 0. This ensures that data in memory is accessed on a boundary the same size as the data type.

Since Virtual Boy maps the I/O bus to the memory bus, the input instructions access the same data as the load instructions. They're nearly identical in function, except the input instructions zero-extend the data being read whereas the load instructions sign-extend it.

The number of cycles taken by load instructions depends on prior bus activity:

^[note] Editor's Note: The V810 documentation uses the phrase "many cycles" with regards to a one-cycle load operation, but it doesn't explicitly define exactly how many is "many". Logic suggests that the instruction needs only take long enough for the pipeline to ready the load operation with its effective address, then can immediately execute it when the long instruction finishes. Either way, this needs some research.

Editor's Note: The cycle counts for input instructions needs to be researched, as they may be identical to the load instructions' counts.

Editor's Note: While the number of CPU cycles taken for an input or load instruction may be small, the actual amount of time taken depends on the speed of whatever is being accessed on the bus (video memory, WRAM, etc.). The exact latencies for reads needs to be researched.

Store and Output

Halfword operations will mask the lowest bit of the effective address to 0, and word operations will mask the two lowest bits to 0. This ensures that data in memory is accessed on a boundary the same size as the data type.

Since Virtual Boy maps the I/O bus to the memory bus, the output instructions access the same data as the store instructions. They're identical in function.

The number of cycles taken by store instructions depends on prior bus activity:

Editor's Note: The cycle counts for output instructions needs to be researched, as they may be identical to the store instructions' counts.

Editor's Note: While the number of CPU cycles taken for an output or store instruction may be small, the actual amount of time taken depends on the speed of whatever is being accessed on the bus (video memory, WRAM, etc.). The exact latencies for writes needs to be researched.

Arithmetic

Compare operations perform subtraction and update the status flags accordingly, but discard the result.

Division operations produce the arithmetic quotient without any fractional part (round towards zero), and the remainder, which shares the same sign as the dividend. The remainder is first stored into r30, then the result is stored into reg2. If a division is attempted with a divisor of zero, a Zero Division exception will be raised with a code of 0xFF80 and a restore PC of current PC.

The result of multiplication operations is 64 bits in size. The upper 32 bits are first stored into r30, then the lower 32 bits are stored into reg2.

The zero flag (Z) is set when the result of any operation is zero, or is cleared otherwise. For multiply operations, only the lower 32 bits of the result are considered.

The sign flag (S) is a copy of the highest-order bit of the result of any operation. For multiply operations, only the lower 32 bits of the result are considered.

The overflow flag (OV) is set in the following situations, or is cleared otherwise:

The carry flag (CY) is set when addition or subtraction results in unsigned wrap-around, or is cleared otherwise. For example, carry will be set when subtracting an unsigned value from a lesser value.

Bitwise

Arithmetic right shift will produce copies of the highest-order bit when filling from the left. Logical right shift will fill with zeroes.

The zero flag (Z) is set when the result of any operation is zero, or is cleared otherwise.

The sign flag (S) is a copy of the highest-order bit of the result of any operation.

The carry flag (CY) is a copy of the last bit shifted out of the register during a shift operation, or cleared if the shift amount was zero.

CPU Control

If the Bcond instruction's condition as specified by cond in PSW is true, then PC is updated directly. Otherwise, PC advances to the next instruction as usual.

The HALT instruction will cause the CPU to stop all processing until an interrupt is accepted. If all interrupts are masked or disabled, HALT cannot finish and the CPU will be stopped until reset.

Because the lowest-order bit of PC is always clear, the effective addresses of branch and jump instructions will have their lowest bit masked to a 16-bit boundary.

Status flags in PSW will only be modified by the LDSR instruction if PSW itself is the system register being loaded into. Their states are determined directly by the value being loaded.

The resulting exception raised by the TRAP instruction will have a code of (0xFFA0 + vector) and a restore PC of next PC.

The number of cycles taken by Bcond varies depending on whether the branch is taken:

All conditional branch instructions are permutations of the Bcond instruction, just with different values for cond. Each permutation is given its own mnemonic. The following conditions and mnemonics can be checked by the Bcond instruction:

Certain conditions have more than one mnemonic. In these situations, either mnemonic can be used and the two are interchangeable.

The Bcond instruction's cond field uses the same numeric values for each condition as the SETF instruction.

The following numeric codes for system registers are used by the LDSR and STSR instructions:

Attempting to load to a reserved system register will have no effect, and they are all read as zero.

Editor's Note: Research is needed to determine whether a conditional branch with a displacement to the following instruction still take 3 cycles, even though it's equivalent to a non-branch.

Floating-Point

All of the floating-point instructions are stored in Format VII and share a common opcode of 111110. They are identified by their sub-opcode field.

The CVT.SW and TRNC.SW instructions produce an approximate word value from a floating short value. CVT.SW will round to the nearest integer value, wheras TRNC.SW will round toward zero.

The zero flag (Z) is set when the result of any operation is zero, or is cleared otherwise.

The carry flag (CY) and sign flag (S) are both copies of the highest-order bit of the result of any operation.

PSW contains status flags that pertain only to floating-point operations. When a floating-point status condition is met, the corresponding flag is set in PSW, but otherwise will not be modified. The floating-point status conditions are as follows:

Status conditions in the list with an associated code will raise an exception with that code if they are met. They are ordered in the list such that items that appear earlier in the list have higher priority than items that appear later in the list. In the event an instruction satisfies more than one such condition, only the one with the highest priority will be processed and have its corresponding flag set in PSW. Flags are set in PSW prior to raising an exception.

Editor's Note: The overflow condition appears to process the result as usual, updating FPR and reg2 as appropriate, then raises the overflow exception when writing the exponent field. Research is needed to determine exactly which values are produced in this situation.

Editor's Note: While the V810 documentation gives ranges for the number of cycles taken for each floating-point instruction, it does not give specifics about which situations result in which cycle counts. Research is needed to determine how long any given operation will take.

Bit Strings

Overview

Bit strings are contiguous sequences of bits in memory. Operations can be performed on one or two bit strings.

Bit strings are defined with three parameters:

Data storage for bit strings follows the order of least-significant to most-significant for bits within words, and by memory address for words. If a bit string extends higher than bit 31 of word address 0xFFFFFFFC or lower than bit 0 of word address 0x00000000, the following bit will wrap around to the other end of the address space.

Registers r26 through r30 are used to define bit strings:

Search operations use the registers designated for the "source" bit string.

Bit string operations are carried out in either an "upward" or "downward" direction. In an upwards operation, the offset of bits within a word increases and the words in memory increase in address. Conversely, a downward operation observes decreased bit offsets and word addresses.

All of the bit string instructions are stored in Format II and share a common opcode of 011111. They are identified by their sub-opcode field.

Bitwise

These operations read from the source bit string and store new bits into the destination bit string, performing the specified operation on the corresponding bits from both strings to produce the final output bits. All of these instructions will clear the 2 lowest-order bits in r30 and r29, and clear the 27 highest-order bits in r27 and r26.

When a bit string instruction is invoked, it will process one word of output and complete. Only after the entire bit string has been processed will PC be advanced to the next instruction. During each invocation, the values in registers r26 through r30 are updated to reflect the current state. This implementation facilitates the handling of interrupts even in the midst of time-consuming bit string operations.

After a bit string instruction fully completes, the source and destination bit strings as specified by registers r30/r27 and r29/r26 respectively will represent the next higher bit in memory. r28 will be zero, as there are no bits remaining to be processed.

During each invocation of a bit string instruction, all of the bits for the current destination word are processed, leaving the following destination word to begin at bit offset zero (as specified by r26). In this way, the destination bit string is processed in full word units across the minimum number of write accesses.

If the source and destination bit strings overlap and the destination bit string begins later than the source bit string, then the source bit string may become corrupted by overwriting data as output before reading it as input. Due to read buffering in the CPU, this will only occur during an invocation of a bit string instruction when the destination bit string begins 64 or more bits after the source bit string.

Editor's Note: The V810 manual provides a table of cycle timings for various configurations of these operations that needs to be incorporated into this document.

Search

These operations scan through the source bit string in the specified direction for a bit with the specified state. At the start of processing, the zero flag (Z) is set and is only cleared if the specified bit was found. All of these instructions will clear the 2 lowest-order bits in r30 and clear the 27 highest-order bits in r27.

When a search instruction is invoked, it will process one word of input and complete. Only after the entire bit string has been processed will PC be advanced to the next instruction. During each invocation, the values in registers r27 through r30 are updated to reflect the current state. This implementation facilitates the handling of interrupts even in the midst of time-consuming search operations.

During each invocation of a search instruction, all of the bits for the current source word are processed, leaving the following source word to begin at bit offset zero (if upward) or 31 (if downward), specified by r27. In this way, the source bit string is processed in full word units across the minimum number of read accesses.

r29 is incremented for each bit processed during a search that does not match the specified bit. It is not modified prior to operation.

After a search instruction fully completes, the source bit string specified by registers r30 and r27 will point to the next bit in memory in the specified direction that follows the matched bit (if a match is found) or the entire string (if no match is found). Register r28 will contain the number of remaining bits in the bit string including the one pointed to by r30 and r27.

Editor's Note: The V810 manual provides a table of cycle timings for various configurations of these operations that needs to be incorporated into this document.

Miscellaneous

CAXI - Compare and Exchange Interlocked

This instruction facilitates synchronization between multiple processors. It has four operands:

When executing this instruction, the following algorithm is carried out:

The program can check the zero flag (Z) to determine what action was taken.

Virtual Boy only has one processor, so the CAXI instruction has limited utility.

SETF - Set Flag Condition

Tests a condition in PSW. If the condition is true, stores 0x00000001 into reg2; otherwise, stores 0x00000000 into reg2.

The purpose of SETF is to provide a means for evaluating simple conditional operations without performing a branch via Bcond. Branching disrupts the pipeline flow and takes more cycles than the corresponding SETF implementations for such operations. For example, either-or assignments such as absolute value and sign benefit from the use of SETF.

The cond field is 4 bits in size. The following conditions can be checked:

Certain conditions have more than one mnemonic. In these situations, either mnemonic can be used and the two are interchangeable.

The cond field uses the same numeric values for each condition as the Bcond instruction.

Nintendo

Standalone

These instructions have unique opcodes.

These instructions facilitate manipulation of the ID flag in PSW through a mechanism that is simpler than using the LDSR and STSR instructions.

Editor's Note: These instructions were borrowed from the 6502/65816 instruction set used by the NES and SNES. When NEC developed the V830 in 1997, they introduced the EI and DI instructions (Enable Maskable Interrupt and Disable Maskable Interrupt, respectively), which use the same opcodes and perform the same operations as NVC's CLI and SEI instructions. However, EI and DI only take 2 cycles to complete.

Extended

These instructions are stored in Format VII and share a common opcode of 111110. They are identified by their sub-opcode field.

The MPYHW instruction performs a 32-bit signed multiplication. The right-hand operand is produced by sign-extending the lower 17 bits of reg1.

The REV instruction reverses the order of the bits in reg2: the highest-order bit of the input becomes the lowest-order bit of the output and so-on.

Editor's Note: One source suggests that XB and XH must supply r0 in the binary encoding of the reg1 field, or else the behavior is undefined. This could use further testing, as no misbehavior has been observed regardless of the value of reg1.

Assembly Notation

The following conventions, except as described below, apply to all instructions in the official V810 assembly notation:

The following instructions have additional conventions:

The notation for each instruction is as follows:

Opcode Map

Attempting to execute any invalid opcode or sub-opcode will raise an exception with code 0xFF90 and a restore PC of current PC.

Bit string instructions are stored in Format II and share a common opcode of 011111. They are identified by their sub-opcode field.

Floating-point and Nintendo instructions are stored in Format VII and share a common opcode of 111110. They are identified by their sub-opcode field.

Communication Port

Contents
Overview
Pinout
Communication Control
Signal Control
Data Registers
Communication Interrupt

Overview

On the underside of the Virtual Boy unit, next to the controller port, is a port labeled "EXT." that can be used for communication between two linked Virtual Boys. Although a link cable was developed for use with the system, no commercial games made use of it and the cable itself was never made available to consumers.

Communication exchanges 8 bits at a time between Virtual Boy units. Bits come from dedicated data registers for transmitted and received data.

The hardware controls the entire communication operation, exchanging bits at a rate of 50 KHz per bit for a total of 160 µs. When the operation completes, a communication interrupt can be configured to be raised.

An additional auxiliary signal can be used for negotiating communication status independently from the actual bits sent and received.

Pinout

The following diagram depicts the pin configuration of the communication port when looking into it from the bottom of the Virtual Boy unit:

The pins have the following significance:

Within a link cable, pins are connected to each end in the following way:

Communication Control

The primary communication operation is performed through the data registers and a single control register:

The primary function of the communication port is to exchange 8 bits of data between two Virtual Boy units. The hardware performs the operation when requested, sending the data in CDTR and receiving data into CDRR.

If C-Int-Inh is clear when the communication operation completes, a communication interrupt is raised.

C-Clk-Sel determines the communication clock signal to use for synchronizing communication operations:

When C-Start is set, a communication operation is initiated. If the external clock is selected, the unit will wait for a communication signal from a linked unit before performing the operation. If the internal clock is selected, the operation begins immediately. When the operation completes, the bits received from the other unit will be loaded into CDRR.

If the internal clock is selected and C-Start is set without another unit waiting for an external clock, a peerless communication will be performed immediately and the bits in CDRR will be undefined.

C-Stat is set as soon as C-Start is set, and will remain set until the communication operation completes. If C-Start is set while C-Stat is already set, nothing happens.

Changing the clock selection while C-Stat is set will not abort the communication operation, but will merely change the clock signal source. If both units are waiting for an external clock and one changes to the internal clock (with or without writing to C-Start) the communication will be carried out normally.

A communication operation cannot be canceled once initiated. The only way C-Stat will be cleared is when the operation completes.

Signal Control

An auxiliary signal channel is present on the communication port intended for use in negotiations between peers. It is managed through a single register:

There are two bits in CCSR that are managed by the hardware:

If there is no second unit connected, the values of CC-Rd and CC-Smp are processed as though a connected unit had the same CCSR configuration.

When a communication operation completes and CC-Smp is updated, its value is compared with CC-Int-Lev. If the two bits match, the interrupt condition is satisfied and will be raised if CC-Int-Inh is clear.

Data Registers

When performing communication operations via CCR, the data transmitted and received is loaded/stored in dedicated registers:

Both of these registers are 8 bits of software-assigned data. CDTR is read/write and CDRR is read-only.

Communication Interrupt

When a communication operation via CCR completes, two interrupts can be optionally raised:

Under either situation, an interrupt will be requested on the CPU with a code of 0xFE30. Each situation is capable of independently requesting an interrupt, and must be acknowledged individually. To acknowlege each type of communication iterrupt:

Game Pad

Contents
Layout
Pinout
Game Pad Control
Data Registers

The game pad is an 8-direction, 6-buton controller that also supplies power to the system. It was manufactured with a battery pack that accepted 6 AA batteries, and an A/C adapter was sold separately. The button state can be read from the controller either through software or through a hardware function, and an interrupt can be configured to raise when a button is pressed.

Layout

The game pad has the following input configuration:

The game pad is responsible for supplying power to the system. On the back of the game pad is a bracket that can hold a power source, which could be either a pack of 6 AA batteries or an A/C wall adapter.

Pinout

The following diagram depicts the pin configuration of the game pad port when looking into it from the bottom of the Virtual Boy unit:

The pins have the following significance:

Game Pad Control

Button state information is read from the game pad one bit at a time over a serial port. There are two signals that control this operation: one to reset the entire process and one to clock the bits being sent back to the console. This process of reading button state information can be handled either by the program or by a hardware function.

All game pad operations are managed through a single register:

Software Read

Setting Para/Si sends a latch signal to the game pad that resets the button read operation. This bit should be cleared when subsequently using Soft-Ck, or else the operation will be repeatedly reset.

To perform a software read, set Para/Si once to reset the operation, then write alternating states for Soft-Ck 16 times. After the 16th bit has been clocked, the data registers will contain the button state bits. Before the 16th bit has been clocked, the contents of the data registers will be undefined.

Writing to Soft-Ck sends the inverse bit to the game pad (0 becomes 1 and vice-versa). In order to properly read the button state, the game pad must receive a 0 followed by a 1 for each button for a total of 33 writes to Soft-Ck.

Editor's Note: If the ambient humidity is high enough, an assembly-optimized software read routine will attempt to process game pad bits so fast that the game pad will respond with unstable data. A dummy MUL instruction between bits seems to add enough latency to address this problem, but may or may not be sufficient in all cases.

Hardware Read

Setting HW-SI will initiate a hardware read operation, which will handle the latch and clock signals automatically. When the operation completes, the data registers will contain the button state bits. Setting HW-SI while a hardware read operation is already underway will have no effect.

HW-SI is always set when read.

While a hardware read operation is underway, SI-Stat will be set. When the operation completes, SI-Stat will be clear.

Setting S-Abt/Dis during a hardware read operation will cancel it immediately.

The hardware read operation clocks buttons at a rate of 31.25 KHz per button for a total of 512 µs. This is significantly slower than the speeds that can be achieved through a software read.

Key Input Interrupt

When a hardware read operation completes and K-Int-Inh is clear, an interrupt will be raised if any bit in the data registers from 15 through 4 is set, but will not be raised if any bit from 3 through 1 is set. Since the standard Virtual Boy controller always sets bit 1, it is impossible for it to raise a key input interrupt.

The key input interrupt has a code of 0xFE00.

Data Registers

After reading button state information from the game pad, a 16-bit value is loaded into two read-only registers, one for the lower 8 bits and one for the higher 8 bits: