Game.com - Sacred Tech Scroll

Overview
Memory Map
System Reset
About
Change Colors

System Components
CPU - SM8521 CPU Core

Game.com is essentially a Sharp SM8521 single-chip microcomputer with a display, speaker and user inputs. This document usually refers to the SM8521 specifically, but pertains to the Game.com system in the general sense.

Memory Map

There SM8521 memory bus is 16 bits in size and is organized by memory type:

RAM is built-in, general-purpose working memory. It can be used for all read and write operations by the CPU.

VRAM is built-in memory used to display images. It is write-only from the perspective of the CPU.

Editor's Note: Research is needed to determine what gets read by the CPU from VRAM.

Editor's Note: Research is needed to determine how the extended RAM region is used, if at all.

Register File

The register file contains system control registers, I/O ports and the CPU registers (which are memory-mapped). It has the following contents:

ROM

Read-only memory (ROM) is non-volatile memory that serves as the source for data assets and program code. ROM is partitioned into 8 KiB banks, up to 5 of which are mapped into the memory bus at any given time in the ROM address range 0x1000 - 0x9FFF.

ROM is managed through the following registers:

All five registers are read/write and store an unsigned 8-bit bank number. The bank number specifies the index of the 8 KiB portion of the ROM data, where bank 0 is the first 8 KiB of the data and so-on. The maximum size of ROM when containing all 256 banks is 2 MiB.

ROM banks 0 through 31 correspond to a 256 KiB internal system ROM and banks 32 through 255 correspond to cartridge ROM. Bank 32 still begins after the first 256 KiB of cartridge ROM, rendering that data inaccessible. Cartridges with less than 2 MiB of ROM may still be able to represent their full contents through address mirroring.

Each register controls a different subset of the ROM address range:

At system reset, addresses 0x1000 - 0x1FFF are mapped to an internal 4 KiB ROM that contains a boot program. The first time MMU0 is written, regular ROM mapping takes over and the boot ROM can no longer be accessed until the next reset.

Editor's Note: Research is needed to determine the ROM mapping at 0x0000 - 0x0FFF while the boot ROM is active. According to the initial value of MMU0, it should be the lowest 4 KiB of system ROM bank 0.

CPU - SM8521 CPU Core

Overview
Specifications
Register Set
Operands

Instruction Set
Memory and Register
Arithmetic
Bitwise
Jump and Control

Appendix
Opcode Map

Specifications

The CPU core of the SM8521 is called SM85CPU:

Although it shares its name with the CPU cores of other SM8500 series computers, the SM8521 CPU core has unique features.

Register Set

All CPU registers except PC are mapped to a region of memory called the register file. Register operations will act on the corresponding values in memory, and memory operations can affect the contents of CPU registers.

The following registers are present:

General-Purpose

There are 16 bytes designated as general-purpose registers, on which most CPU instructions operate. They can be used in any context—be it 8- or 16-bit—such as in arithmetic operations, as memory addresses, etc.

When being used as 8-bit registers, the general-purpose registers are named r0 through r15. When being used as 16-bit register pairs, they are named rr0 through rr14 (even numbers only) and combine both the numbered byte and the following byte.

The RP field in PS0 can be used to relocate the 16 bytes of general-purpose registers to places other than their default position in the register file.

PC - Program Counter

Holds the address of the instruction about to be executed. PC is automatically incremented as instruction bytes are fetched from memory.

PS0 - Processor Status 0

Configures high-level settings for the processing of general-purpose registers and masking of interrupts. Is a byte with the following format:

RP is the register pointer and specifies the base address of the general-purpose registers in memory. Shift the value of RP left by 3 bits to yield the bus address of the general-purpose registers, where the default is 0 and the high-order bits are all clear.

IM is the interrupt mask and specifies which interrupt levels are masked (ignored). Is one of the following values:

PS1 - Processor Status 1

Contains conventional status flags. Is a byte with the following format:

During the operation of the branch and call instructions, certain flag state combinations are checked in PS1.

SP - Stack Pointer

Points to the most recent data added to the stack.

The SPC field in SYS can be used to configure whether SP functions as an 8-bit or 16-bit register. When acting as an 8-bit register, the highest 8 bits of stack addresses are treated as clear.

The individual bytes of SP may be referenced as SPH for the high 8 bits or SPL for the low 8 bits.

Editor's Note: Research is needed to confirm that the high bits of stack addresses are clear when SPC is clear.

SYS - System Configuration Register

Configures auxiliary system features. Is a byte with the following format:

When SPC is clear, the upper 8 bits of stack addresses are treated as clear.

MCNF controls the expansion memory at addresses 0x1000 - 0xFFFF. Must be one of the following values:

Editor's Note: Research is needed to determine whether the - bits actually do anything.

Editor's Note: Research is needed to confirm that the high bits of stack addresses are clear when SPC is clear.

Editor's Note: Research is needed to determine what happens when accessing expansion memory while MCNF=0.

Editor's Note: Research is needed to determine what happens for other values of MCNF.

Operands

An instruction's operands specify the target(s) of the operation. When multiple operands are present, the operation's destination is listed on the left and the source(s) on the right. Depending on the instruction, data for different kinds of operands may be present, encoded directly into the instruction's machine code.

Editor's Note: Research is needed to determine whether RP affects only 3-bit indexed operands or all register file accesses in the 0x00 - 0x0F range.

Operands
3-Bit Register Indexes
Condition
Register
Register Pair
Register File
Register Pair File
Register Indirect
Register Pair Indirect
Register Indirect Auto Increment
Register Pair Indirect Auto Increment
Register Indirect Auto Decrement
Register Pair Indirect Auto Decrement
Register Index
Register Pair Index
Index Indirect
Immediate
Immediate Long
Bit
Relative
Direct
Direct Short
Direct Special Page
Direct Indirect

3-Bit Register Indexes

Many instructions specify general-purpose registers or register pairs using 3-bit fields to reduce the required space used. The values of these 3-bit fields correspond to the following registers and register pairs:

Condition

The BR and JMP instructions can conditionally move the program flow to another address depending on certain combinations of flags in PS1. Condition codes are 4 bits:

Certain conditions have more than one mnemonic. In these situations, either mnemonic can be used and the two are interchangeable.

Register
Register Pair

Specifies a general-purpose register or register pair using a 3-bit register index, and accesses the value in the register.

Notation:

Register File
Register Pair File

Specifies an 8-bit address in the register file, and accesses the 8- or 16-bit value in memory. When specifying a register pair, the address must be even.

Notation:

Editor's Note: Research is needed to determine what happens if a register file pair operand has the lowest bit set. The assembler refuses to process these.

Register Indirect
Register Pair Indirect

Specifies a general-purpose register or register pair using a 3-bit register index, regards the value in the register as an address, and accesses the 8- or 16-bit memory at that address.

Notation:

Register Indirect Auto Increment
Register Pair Indirect Auto Increment

Specifies a general-purpose register or register pair using a 3-bit register index, regards the value in the register as an address, accesses the 8- or 16-bit memory at that address, then increases the value in the register by 1.

Notation:

Editor's Note: Research is needed to confirm or correct this addressing mode's operation.

Register Indirect Auto Decrement
Register Pair Indirect Auto Decrement

Specifies a general-purpose register or register pair using a 3-bit register index, decreases the value in the register by 1, regards the new value in the register as an address, then accesses the value in memory at that address.

Notation:

Editor's Note: Research is needed to confirm or correct this addressing mode's operation.

Register Index
Register Pair Index
Index Indirect

Specifies a general-purpose register or register pair using a 3-bit register index and a signed 8- or 16-bit displacement offset, regards the sum of the value in the register and the displacement offset as an address, then accesses the value in memory at that address.

Notation:

If the displacement offset is zero, n(r) may be written as @r and nn(rr) may be written as @rr.

The Index Indirect version of this operand type specifies an 8-bit general-purpose register and a 16-bit displacement offset. As this operand type is used only by the CALL and JMP instructions, the leading @ character indicates that the target code is at the address given by the value loaded from memory.

r0 and rr0 cannot be used with this operand type.

Editor's Note: What would be the binary coding for n(r0) when used by BBC and BBS is instead interpreted as direct special page. It is not possible for the CPU to use r0 with this operand type.

Editor's Note: What would be the binary codings for nn(rr0) and @nn(r0) are instead interpreted as direct indirect. It is not possible for the CPU to use r0 or rr0 with this operand type.

Editor's Note: Research is needed to determine why n(r0) is prohibited for instructions other than BBC and BBS. It is rejected by the assembler, but doesn't appear to correspond to any alternate addressing mode.

Immediate
Immediate Long
Bit

Specifies a literal numeric value for the operand.

Notation:

#number

Immediate specifies an 8-bit number and Immediate Long a 16-bit number. Bit specifies a 3-bit number that represents the position of the bit of interest within its byte of data.

Relative

Specifies an 8-bit signed displacement offset to add to PC to compute the address of the next instruction. The value to use for PC in the computation is the address of the byte following the current instruction.

Notation:

RA

The operand is most commonly displayed to the user as the computed or symbolic destination rather than the displacement offset.

Direct
Direct Short
Direct Special Page
Direct Indirect

Specifies a direct address.

Notation:

The data at the destination of this operand type depends on the instruction being used.

For Direct Short, the address is formed by taking 0x1000 and adding to it 12 bits that are encoded into the instruction code.

For Direct Special Page, the address is formed by taking 0xFF00 and adding to it 8 bits that are encoded into the instruction code.

The address ultimately represented by the Direct Indirect version of this operand type is the 16-bit value located at the address given by the operand.

Memory and Register

Instructions

BCLR - Bit Clear

Clears the state of a bit in memory to 0.

BMOV - Bit Move

Moves a bit value into the bit flag (B) or memory.

BSET - Bit Set

Sets the state of a bit in memory to 1.

CLR - Clear

Sets a value in memory to 0.

CLRC - Clear Carry Flag

Clears the carry flag in PS1.

MOV - Move

Takes the byte value from src and stores it into dest.

The final variant of this instruction specifies a destination with a 3-bit field, as follows:

MOVM - Move Under Mask

Takes the byte value from dest, takes the bitwise AND of it with the mask value, takes the bitwise OR of the result and src, and stores the result into dest.

MOVW - Move Word

Takes the word value from src and stores it into dest.

POP - Pop from Stack

Retrieves an 8-bit value from the stack and stores it in the operand. During a pop operation, the value is loaded from the memory pointed to by SP, then SP is incremented by 1.

POPW - Pop Word from Stack

Retrieves a 16-bit value from the stack and stores it in the operand. During a pop operation, the value is loaded from the memory pointed to by SP, then SP is incremented by 2.

PUSH - Push to Stack

Stores an 8-bit value on the stack. During a push operation, SP is decremented by 1, then the value is stored into memory at the address pointed to by SP.

PUSHW - Push Word to Stack

Stores a 16-bit value on the stack. During a push operation, SP is decremented by 2, then the value is stored into memory at the address pointed to by SP.

SETC - Set Carry Flag

Sets the carry flag (C) to 1.

SWAP - Swap Nibbles

Exchanges the nibbles in the operand byte.

Arithmetic

Instructions

ADC - Add with Carry

Adds the two operands, plus 1 more if the carry flag (C) was set, and stores the result into dest.

ADCW - Add Word with Carry

Adds the two operands, plus 1 more if the carry flag (C) was set, and stores the result into dest.

ADD - Add

Adds the two operands and stores the result into dest.

ADDW - Add Word

Adds the two operands and stores the result into dest.

BCMP - Bit Compare

Compares the bit flag (B) with a bit in memory.

CMP - Compare

Subtracts the operands, updating the status flags in the process, and discards the result.

CMPW - Compare Word

Subtracts the operands, updating the status flags in the process, and discards the result.

DA - Decimal Adjust

Editor's Note: Research is needed to determine the exact operation of this instruction. Its apparent use is to correct for BCD after addition or subtraction.

DEC - Decrement

Subtracts 1 from the operand, storing the result into dest.

DECW - Decrement Word

Subtracts 1 from the operand, storing the result into dest.

DIV - Divide

Performs a division on the 16-bits of dest by the low 8 bits of src. The 16-bit quotient is stored into dest and the 8-bit remainder is stored into the high 8 bits of src.

Editor's Note: Research is needed to determine the exact operation of this instruction. One source suggests the following: 1) the division is signed, 2) if the divisor is zero, V is set and no operation or exception occurs, and 3) if src is immediate, the remainder is discarded.

EXTS - Extend Sign

If bit 7 of dest is clear, the upper 8 bits of dest are cleared. Otherwise, the upper 8 bits of dest are set. The result is stored into dest.

INC - Increment

Adds 1 to the operand, storing the result into dest.

INCW - Increment Word

Adds 1 to the operand, storing the result into dest.

MULT - Multiply

Multiplies the low 8 bits of dest by src and stores the 16-bit result into dest.

Editor's Note: Research is needed to determine the exact operation of this instruction. One resource suggests that the multiplication is signed.

NEG - Negate

Calculates the additive inverse of dest by subtracting dest from zero, and stores the result back into dest.

SBC - Subtract with Carry

Subtracts the two operands, minus 1 more if the carry flag (C) was set, and stores the result into dest.

SBCW - Subtract Word with Carry

Subtracts the two operands, minus 1 more if the carry flag (C) was set, and stores the result into dest.

SUB - Subtract

Subtract the two operands and stores the result into dest.

SUBW - Subtract Word

Subtracts the two operands and stores the result into dest.

Bitwse

Instructions

AND - Logical And

Computes the bitwise AND of the operands. The result is stored in dest.

ANDW - Logical And Word

Computes the bitwise AND of the operands. The result is stored in dest.

BAND - Bit And

Computes the bitwise AND of the Bit flag (B) and the operand. The result is stored in B.

BOR - Bit Or

Computes the bitwise OR of the Bit flag (B) and the operand. The result is stored in B.

BTST - Bit Test

Computes the bitwise AND of the operands, updating the status flags in the process, and discards the result.

BXOR - Bit Exclusive Or

Computes the bitwise exclusive OR of the Bit flag (B) and the operand. The result is stored in B.

COM - Complement

Inverts the bits of dest and stores the result back into dest.

COMC - Complement Carry Flag

Inverts the carry flag (C).

OR - Logical Or

Computes the bitwise OR of the operands. The result is stored in dest.

ORW - Logical Or Word

Computes the bitwise OR of the operands. The result is stored in dest.

RL - Rotate Left

Performs a left bitwise rotation on dest by 1 bit and stores the result into dest.

RLC - Rotate Left through Carry

Forms a 9-bit value by taking dest as the lowest 8 bits and the carry flag (C) as the highest bit, performs a left bitwise rotation on this value by 1 bit, and stores the result into C (high 1 bit) and dest (low 8 bits).

RR - Rotate Right

Performs a right bitwise rotation on dest by 1 bit and stores the result into dest.

RRC - Rotate Right through Carry

Forms a 9-bit value by taking dest as the lowest 8 bits and the carry flag (C) as the highest bit, performs a right bitwise rotation on this value by 1 bit, and stores the result into C (high 1 bit) and dest (low 8 bits).

SLL - Shift Left Logical

Performs a left bitwise shift on dest by 1 bit and stores the result in dest.

SRA - Shift Right Arithmetic

Performs a sign-propagating right bitwise shift on dest by 1 bit and stores the result in dest. The state of the highest-order bit will not change.

SRL - Shift Right Logical

Performs a zero-filling right bitwise shift on dest by 1 bit and stores the result in dest. The highest-order bit will be cleared.

XOR - Logical Exclusive Or

Computes the bitwise exclusive OR of the operands. The result is stored in dest.

XORW - Logical Exclusive Or Word

Computes the bitwise exclusive OR of the operands. The result is stored in dest.

Jump and Control

Instructions

BBC - Branch on Bit Clear

Tests a bit in memory. If the bit is clear, a jump is performed by adding a signed displacement offset to PC.

BBS - Branch on Bit Set

Tests a bit in memory. If the bit is set, a jump is performed by adding a signed displacement offset to PC.

BR - Branch

Tests a combination of flags in PS1. If the condition is true, a jump is performed by adding a signed displacement offset to PC.

If T is specified as the condition, the condition operand does not need to be written.

CALL - Call Subroutine

Calls a subroutine by saving the return address to the stack and updating PC to the address of the subroutine.

CALS - Call Short Subroutine

Calls a subroutine by saving the return address to the stack and updating PC to the address of the subroutine.

DBNZ - Decrement and Branch on Non-Zero

Subtracts 1 from src and stores the result into src. If the new value of src is not zero, a jump is performed by adding a signed displacement offset to PC.

DI - Disable Interrupt

Clears the Interrupt Enable flag (I), thereby masking interrupts.

DM - Unknown

Editor's Note: The operation of this instruction is unknown. The assembler does not produce its opcodes for any inputs, and its existence is known only from a disassembler that was part of the SDK. Research is needed to determine what this instruction does.

EI - Enable Interrupt

Sets the Interrupt Enable flag (I), thereby permitting interrupts.

HALT - Move to HALT Mode

Suspends the CPU until an interrupt is requested. After an interrupt is requested (which may result in a handler routine ending with IRET), execution will continue at the instruction following the HALT instruction.

IRET - Return from Interrupt

Returns from an interrupt handler. The program will resume from wherever it left off: either the instruction following the instruction that raised the exception, or the instruction that would have been executed had an interrupt not occurred.

JMP - Jump

Stores dest into PC, optionally after testing a combination of flags in PS1. If a condition is tested and is false, PC will not be changed.

If T is specified as the condition, the condition operand does not need to be written.

NOP - No Operation

No action is performed.

RET - Return from Subroutine

Returns from a subroutine, restoring PC to the location when the subroutine was first called.

STOP - Go to STOP Mode

Suspends most components of the system until an interrupt is requested. After an interrupt is requested (which may result in a handler routine ending with IRET), execution will continue at the instruction following the STOP instruction.

Editor's Note: Research is needed to determine what components are suspended by this instruction.

Opcode Map

System Reset

System components are initialized in the following ways when the Game.com is powered on.

CPU

The following registers are initialized on reset:

All other CPU registers have undefined contents on reset.

Memory Map

The following registers are initialized on reset:

Additionally, a 4 KiB internal boot ROM is mapped to addresses 0x1000 - 0x1FFF after reset.

About

Game.com - Sacred Tech Scroll
March 10, 2023
Written by Guy Perfect

Special thanks to the following individuals:

References

SM8521
Written by Sharp Corporation
Download

Sharp Micro Controller SM85 Series Macro Assembler
Version 1.10
Created by Sharp Corporation

Dumping Tiger Game.com ROMs
April 1, 2019
Article detailing the dumping process
Written by Kao
Link

March 10, 2023