WonderSwan - Sacred Tech Scroll

Overview
Memory Map
I/O Map
Open Bus
Cartridge
ROM Header
Hardware Architecture
System Reset
About
Change Colors

System Components
CPU - V30MZ/V Series Microprocessor
DMA - Direct Memory Access
LCD Panel
Sound
Keypad
Serial EEPROM
RTC - Real-Time Clock

Memory Map

The WonderSwan memory bus is 20 bits wide and is organized by memory type:

Physical Addresses

Because the CPU registers are 16-bit and the bus is 20-bit, multiple registers are needed to represent a complete physical address. This is achieved through the use of the segment registers.

When constructing a physical address, one register is used normally as a 16-bit value called the offset. A second value called the segment is then produced by taking the value in the appropriate segment register and shifting it left 4 bits. This shifted segment value is then added to the offset to produce the final 20-bit physical address.

Physical addresses are a maximum of 20 bits wide. If the computation of a physical address exceeds 0xFFFFF, the value will wrap back around to 0x00000 and continue up from there.

Unaligned Accesses

If a 16-bit memory access is performed on an odd offset (the lowest bit is set), it is silently converted into two 8-bit accesses instead. In this situation, one additional CPU cycle is spent. The physical address is computed independently for each byte, with the offset being incremented for the second byte before incorporating the bits from the segment. For this reason, any 16-bit access with an offset of 0xFFFF will access two non-consecutive bytes in memory.

WRAM

WRAM is built-in, general-purpose working memory. The size of WRAM varies depending on whether or not color mode is enabled:

WRAM is further organized as follows:

Cartridge SRAM

Some cartridges contain save RAM (SRAM), which is volatile memory that is typically made persistent via a battery for use with games requiring save functionality. SRAM is partitioned into 64 KiB banks, one of which is mapped onto the memory bus at any given time in the SRAM address range 0x10000 - 0x1FFFF.

Memory mapping for SRAM is managed through the following I/O ports:

All 8 bits of RAM_BANK and RAM_BANK_L, and the lowest 2 bits of RAM_BANK_H, can be managed by the program. The upper 6 bits of RAM_BANK_H are clear when read.

On the 2001 mapper, the bank setting is 8-bit and is taken from RAM_BANK. On the 2003 mapper, RAM_BANK is a mirror of RAM_BANK_L, and the bank setting is 10-bit and is formed by the combination of RAM_BANK_H for the high bits and RAM_BANK_L for the low bits.

When accessing SRAM, the 20-bit physical address is transformed into a 32-bit offset into the cartridge memory. The lower 16 bits of the cartridge offset are taken from the lower 16 bits of the physical address. The upper 16 bits of the cartridge offset are taken from RAM_BANK or RAM_BANK_H and RAM_BANK_L as described above.

The implementation silently converts word accesses in the cartridge SRAM range into consecutive pairs of byte accesses, adding one additional CPU cycle in the process. The SRAM interface is 8-bit, so it cannot be used with the DMA feature.

During system reset, these ports are initialized with 0xFF. After mirroring, this corresponds to the last bank of SRAM data.

Cartridge ROM

Read-only memory (ROM) is non-volatile cartridge memory that serves as the source for data assets and program code. ROM is partitioned into 64 KiB banks, up to 14 of which are mapped onto the memory bus at any given time in the ROM address ranges 0x20000 - 0xFFFF.

Memory mapping for the 0x20000 - 0x2FFFF and 0x30000 - 0x3FFFF address ranges is managed through the following I/O ports:

All 8 bits of all six ports can be managed by the program. The "_0" ports control which ROM bank is mapped to the 0x20000 - 0x2FFFF address range and the "_1" ports control which ROM bank is mapped to the 0x30000 - 0x3FFFF address range.

On the 2001 mapper, the bank setting is 8-bit and is taken from ROM_BANK_0 or ROM_BANK_1. On the 2003 mapper, ROM_BANK_0 and ROM_BANK_1 are mirrors of ROM_BANK_0_L and ROM_BANK_1_L respectively, and the bank setting is 16-bit and is formed by the combination of the appropriate "_H" port for the high bits and the "_L" port for the low bits.

When accessing ROM in these ranges, the 20-bit physical address is transformed into a 32-bit offset into the cartridge memory. The lower 16 bits of the cartridge offset are taken from the lower 16 bits of the physical address. The upper 16 bits of the cartridge offset are taken from the corresponding "ROM_BANK_" or "_H" and "_L" ports as described above.

During system reset, these ports are initialized with 0xFF. After mirroring, this corresponds to the last bank of ROM data.

Memory mapping for the 0x40000 - 0xFFFFF address range is managed through the following port:

All 20 bits of the physical address contribute to the memory offset into cartridge ROM for this address range. Additional offset bits beginning with bit 20 are taken from LINEAR_ADDR_OFF for a total of 28 bits.

During system reset, this port is initialized with 0xFF. After mirroring, this corresponds to the last 12 banks of ROM data.

I/O Map

The WonderSwan I/O bus is 8 bits wide. The program accesses it through the IN and OUT instructions.

Unaligned Accesses

If a 16-bit port access is performed on an odd address (the lowest bit is set), it is silently converted into two 8-bit accesses instead. In this situation, one additional CPU cycle is spent.

Ports

The following I/O ports are available:

If a port that is not available on the monochrome model is accessed on a color model with color mode disabled, no action will be taken when written and the value 0x90 is always read, simulating the open bus behavior of the monochrome model.

The following port address ranges are handled by the following components:

In most cases, word-size ports can be used with multiple byte accesses. The exception is the internal EEPROM on the monochrome model. Accessing odd internal EEPROM port addresses as bytes will function as open bus, while even port addresses function normally. On color models, byte accesses on odd port addresses function normally even when color mode is disabled.

The implementation silently converts word accesses in the cartridge range into consecutive pairs of byte accesses, adding one additional CPU cycle in the process.

Although the I/O bus is 8 bits wide, the CPU is capable of specifying 16-bit port addresses. Accessing port addresses greater than 0xFF has the following behaviors:

Editor's Note: Port addresses not listed above have no known significance. They are assumed to function as open bus.

Open Bus

When a memory or I/O access is attempted on an address that has no corresponding functionality, nothing happens and the default response of the applicable bus takes effect. This occurrence is known as "open bus".

Open bus occurs in the following situations:

Writing or outputting to open bus has no effect. Reading or inputting from open bus returns a predetermined value. The open bus value is always 0x90 on the monochrome model, and undefined on color models.

On color models with color mode disabled, memory and I/O addresses that are available only when color mode is enabled will simulate the open bus behavior of the monochrome model: they will not respond to writes and they will always read the value 0x90.

Editor's Note: Research is needed to determine the exact open bus values for color models. It is known that they tend to read as 0x00 unless color mode is disabled and the port address is 0x4000 or greater, when they tend to return 0x90 instead. There may be other circumstances that influence the open bus value.

Cartridge

The cartridge inserts into the back of the WonderSwan unit and provides the program and save data for a software title.

Pinout

The following diagram depicts the pin configuration of the cartridge as seen looking at the face of the cartridge with the label upright:

The pins have the following significance:

Pin signals are +3V DC.

The MBC pin is used to authenticate the cartridge's mapper chip on reset using serial communication. The serial clock pin provides a 384 KHz reference signal for this communication as well as communication with an EEPROM if present.

When accessing memory, the Memory/IO pin is +3V and all 20 address pins specify the memory address. When accessing I/O, the Memory/IO pin is 0V, address pins 0 through 7 specify the lower 8 bits of the port address, address pins 8 through 15 are 0V, and address pins 16 through 19 contain a copy of port address bits 4 through 7 respectively.

Reads and writes will only be accepted while both the the cartridge select pin and the corresponding "enable" pin are 0V.

Editor's Note: Research is needed to determine the authentication protocol on pin 41.

Interrupt

The cartridge supports an interrupt that the program can use to respond to cartridge activity. For information regarding software setup, see Managing Interrupts. The cartridge interrupt is called CASETTE and has the relative vector index +2.

Mappers

All WonderSwan cartridges contain a logic circuit that is responsible for selecting banks of cartridge memory to make available to the CPU, and to perform ancillary I/O tasks. These chips are called mappers and two versions were distributed called "2001" and "2003" after their model numbers.

I/O ports with address 0xC0 and greater are handled by the cartridge mapper. Accessing a port address not supported by a mapper results in open bus behavior.

The 2001 mapper supports the following I/O ports:

The 2003 mapper supports the following I/O ports:

ROM Header

At reset, memory addresses FFFF:0000 - FFFF:000F must contain specific kinds of data. Due to the banking behavior of the cartridge mapper, these addresses correspond to the last 16 bytes in cartridge ROM. The significance of these addresses is described below.

The entry point is the address of the first instruction executed by the CPU. The console boot program requires this to be a 32-bit immediate BR instruction with an 0xEA opcode or else the system will not boot.

The maintenance byte has the following format:

BANDAI maintains a list of publisher IDs that is beyond the scope of this document.

The color field may be one of the following values:

The game ID is the binary-coded decimal representation of the last two digits of the product's SKU.

The game version byte has the following format:

ROM size indicates read-only memory present in the cartridge. It has the following known values:

Save type indicates persistent memory present in the cartridge. It has the following known values:

The following flags are known:

The checksum is the cumulative sum of all 8-bit bytes in the ROM‐including the ROM header‐except for the two bytes of the checksum field. This field is not required to be set correctly.

Editor's Note: It is assumed that all bits in the game version byte other than bit 7 belong to the version number, but this has not been verified.

Hardware Architecture

Information about the current hardware is avaiable through the following I/O port:

Inspecting WSC is the preferred way to detect hardware features.

Editor's Note: The program should not change cbus. This bit's writeable status may only be intended for use by the boot ROM.

Editor's Note: Certain bits in this port may be writeable depending on the exact model and color mode configuration, and this may be a side-effect of exposing certain features to the boot ROM. It's apparent that the only intended use of this port by programs is to check for the availability of color mode.

Color Mode

On color models, various features not present in the monochrome model can be activated or deactivated.

Color features are managed through the following port:

This port has no function on the monochrome model, and reading from it on a monochrome model returns undefined data.

If Color is set and FourBpp is clear, characters are treated as 2 bits per pixel.

If Color and FourBpp are both set, characters are treated as 4 bits per pixel. FourBpp has no effect when Color is clear.

If Color, FourBpp and Packed are all set, characters are treated as 4 bits per pixel packed. Packed has no effect when either Color or FourBpp is clear.

Setting Color will enable color mode on color models. The following system features are available only while Color is set:

Some features behave differently depending on whether color mode is enabled or disabled. In all cases, such features will behave the way they do on the monochrome model whenever color mode is disabled. In particular, certain I/O ports have different formats in color mode, and will use the monochrome model's formats whenever color mode is disabled. If color mode is disabled, writes into the expanded WRAM are ignored and reads in expanded WRAM are undefined.

Editor's Note: The WonderWitch API preserves the lowest 5 bits when accessing SYSTEM_CTRL2. No significance has been observed in these bits, so this decision may have been made in the interest of future-proofing it.

Color System

When color mode is available according to SYSTEM_CTRL1, an additional I/O port becomes available:

CPU - V30MZ/V Series Microprocessor

Overview
Specifications
Register Set
Operands
Prefixes

Exceptions
Exceptions and Interrupts
List of Exceptions

Instruction Set
Memory and Register
Arithmetic
Bitwise
CPU Control
Branch
Block
Segment Override

Appendix
Opcode Map
8086 Translation Map

Specifications

WonderSwan uses an NEC V30 CPU:

The V Series microprocessors were designed as pin-compatible alternatives to the Intel 8086. The V30MZ in particular is a later model providing limited compatibility with the 8086 and has reduced capabilities when compared to other V Series products, but offers improved power efficiency and execution time.

Register Set

All registers on the V30MZ are 16-bit. The following registers are present:

AW, BW, CW, DW - General Purpose Registers

Most operations on data, such as arithmetic operations, are performed on these registers. They can also be used as sources and destinations for data transfers.

For 16-bit operations, these registers are used directly as AW, BW, CW and DW.

For 8-bit operations, these registers may be used as two 8-bit registers each. The low-byte registers are used as AL, BL, CL and DL. The high-byte registers are used as AH, BH, CH and DH.

DS0, DS1, PS, SS - Segment Registers

Provide the segment portion of a physical address. The value in the segment register is shifted left 4 bits, and the resulting value is added to the 16-bit offset value of another register to compute the final physical address.

Operations that produce physical addresses have a default segment register assigned to them. In most of these cases, the actual segment register used in the physical address calculation can be changed by using a segment override prefix.

The following are the various memory-access scenarios and how they interact with segment registers:

SP - Stack Pointer

Points to the most recent data added to the stack.

When constructing a physical address, SP provides the offset portion and SS provides the segment portion.

BP - Base Pointer

Serves as a data offset for memory operations, and is used as part of the operation of select stack instructions.

IX, IY - Index Registers

Used as relative offsets during memory operations: one register is used as the base value for the offset, then an index register is added to that value. For instance, if the offset of a data struct is stored in one register, the individual members of that struct could be accessed using an index register.

PC - Program Counter

Holds the offset of the instruction about to be executed. PC is automatically incremented as instruction bytes are fetched from memory. When an instruction is fully fetched, PC will hold the offset of the first byte of the next instruction.

When constructing a physical address, PC provides the offset portion and PS provides the segment portion.

After PC reaches 0xFFFF, it will roll over to 0x0000 without modifying PS.

PSW - Program Status Word

Holds status and configuraiton flags. During the operation of instructions, flags in PSW are used to control some operations and reflect information about the results of other operations.

This register has the following format:

During the operation of the branch instructions, certain flag state combinations are checked in PSW.

DIR and CY can be modified by the CLR1 and SET1 instructions.

IE can be modified by the DI and EI instructions.

There is no instruction that can directly modify BRK. To change it, the "POP PSW" instruction must be used. The exception will be raised after executing the instruction that follows POP PSW.

Editor's Note: On other V Series CPUs, bit 15 of PSW is a flag called "mode" (MD), used to control an 8-bit emulation mode. While set, the CPU would run in native mode, and while clear, it would run in emulation mode. Emulation mode provides a different set of instructions and was intended for backwards compatibility with older processors.

Operands

CPU instructions are encoded using various different binary formats. Depending on the instruction, data for different kinds of operands may be present, encoded directly into the instruction's machine code.

Operands
Operation Size
Operation Direction
Accumulator
Immediate
Memory
Register
Segment Register

Operation Size

Many instructions can operate as either 8-bit or 16-bit. This affects the width of the registers being accessed as well as how many bytes need to be read from memory for operand values. The data size of an operation is often specified in the first byte of instruction code in one of two ways:

When writing instructions, the size of the operation is not explicitly specified: is typically evident from the register name used for a register operand. If a register operand is not present, distinct mnemonics are provided for each operation size.

Operation Direction

Some instructions specify multiple operands as well as the direction in which to perform the operation. The direction of such instructions is specified in the first byte of instruction code:

The operands of an instruction have a default order. Typically, the left operand is the operation's destination and the right operand is a source. If D is present and set, the operands' order and therefore roles are reversed, causing what would normally be the destination to act as the source and vice-versa.

Accumulator

Some instructions implicitly use an "accumulator" register as one of their operands. If the operation is 8-bit, the register is AL, and if the operation is 16-bit, the register is AW.

Immediate

When an instruction's operand is stored directly in the machine code, it is called an immediate operand. Normally, the size of an immediate operand matches the size of the operation. Some specific instructions may have a special bit in the first byte of machine code that influences the format of the immediate operand:

If s is present and clear, the size of the immediate value is the same as that of the operation: either 8 bits or 16 bits.

If s is present and set, the immediate value is always 8 bits. If the operation is 16-bit, the immediate value is sign-extended to 16 bits.

The data for immediate operands appears as additional instruction bytes. 16-bit immediate values are stored with the low byte first.

If the instruction also contains a memory operand, the bytes of the memory operand appear before the bytes of the immediate operand.

Memory

Instructions may specify an operand using fields called Mod and Mem. The operand's value may come from a CPU register, or may be loaded from memory using one of a variety of offset expressions. Mod and Mem collectively describe how to access the operand's value.

Instructions with memory operands begin with 2 bytes, the second of which has the following structure:

Notation: aa---mmm

When Mod is 3, Mem specifies the index of the register containing the operand's value. For more information, see Register.

When Mod is not 3, Mem specifies the base of the expression to use to calculate a memory offset. The value of the operand is then read from this offset. The following expression bases are available:

The offset portion of the operand's physical address is calculated by evaluating the expression base and optionally adding a signed displacement offset to it. The value of Mod determines how this is done:

The default segment register to use when calculating the physical address depends on whether or not BP is present in the offset expression. If BP is present, the default segment register is SS. If BP is not present, the defaut segment register is DS0. The actual segment regsiter used can be specified with a segment override prefix.

If the instruction also contains an immediate operand, the bytes of the memory operand appear before the bytes of the immediate operand.

Editor's Note: Research is needed to determine whether offset expressions contain signed components, or if it even matters. It may be the case that the offset portion of the physical address is entirely computed as 16 bits before incorporating the value of the segment register.

Register

Most instructions specify at least one register as a source or destination operand. The register is identified with a 3-bit index, depending on whether the operation is 8-bit or 16-bit:

If a memory operand has a Mod field of 3, its Mem field will be a register index. In this way, specific instructions can specify two register operands.

Instructions with a register operand usually also have a memory operand, and the register index is encoded into the bits of the second byte not occupied by the memory operand:

Notation: --rrr---

Specific instructions with register operands may instead specify the register index in the first byte of instruction code:

Notation: -----rrr

Segment Register

Some instructions specify a segment register as the source or destination of a data transfer. The segment register is identified with a 2-bit index:

In all cases where a segment register operand is encoded into an instruction's bits, the register index occupies the middle two bits of the byte in which it appears:

Notation: ---rr---

The POP and PUSH instructions may encode the segment register index into the first byte of instruction code.

The MOV instruction may encode the segment register index into the second byte of instruction code, shared with the bits of a memory operand. In this situation, bit 5 of that byte is not used.

Editor's Note: Research is needed to verify that bit 5 is not used in an instance of MOV with a segment register operand.

Prefixes

The behavior of CPU instructions can be modified by prepending prefixes to the instruction. Prefixes are one-byte codes that specify alternative instruction functionality, and appear in the program code immediately prior to the bytes of the prefixed instruction.

There are three general categories of prefixes. All prefixes within each category are mutually exclusive with one another:

There is no hard limit on how many prefixes may be attached to an instruction. However, since there are three total categories of prefixes, there can be at most three effective prefixes on one instruction. If multiple prefixes from the same category are attached to the same instruction, only the last one (the one immediately preceding the regular instruction data) will take effect.

After fetching a prefix byte and prior to executing the prefixed instruction, interrupts will not be accepted and the break flag (BRK) will not function.

Exceptions and Interrupts

Certain events can cause the CPU to break its current execution, save its status to the stack and begin execution somewhere else according to what happened. The general term for such an occurrence is exception. When the exception is triggered by another hardware component, it is called an interrupt.

On V30MZ, all exceptions are formally referred to as interrupts. Exceptions that result from CPU operations are referred to as software interrupts.

Exception

Processing of CPU instructions can raise exceptions on their own, known as software interrupts. This can happen in the following situations:

Attempting to execute an instruction with an undefined opcode or sub-opcode does not result in an exception. There is no associated operation, so any bytes used to supply their prefixes, opcode, sub-opcode, memory operand or immediate operand are skipped over.

Editor's Note: Research is needed to determine the number of CPU cycles consumed by an illegal opcode.

Interrupt

Hardware components other than the CPU are allowed to request interrupts. This provides a mechanism to synchronize all system operations as well as a way for a hardware component to signal the program when certain conditions are met.

Interrupts can be disabled by clearing the IE flag in PSW. The EI and DI instructions manipulate this flag directly, and modifications to PSW through other instructions can also be used to configure it.

When an interrupt is requested, it will be processed after the current CPU instruction finishes and before the next instruction begins. There are certain situations in which interrupt requests are not processed between instructions, and in which the break flag (BRK) will not function:

The HALT instruction will stop all CPU activity until an interrupt request occurs, at which point it will resume with exception processing if IE is set, or the next instruction if IE is clear. If no interrupt requests are enabled in any hardware component, the CPU will be suspended until reset.

Vectors

When any exception occurs, the program code responsible for handling it is located by reading the address corresponding to its vector. An exception's vector is an unsigned 8-bit index into a global list of handler addresses.

Exception vectors are located in WRAM at the following addresses:

Up to 256 exception vectors are supported, mostly to be used from software via the BRK instruction.

Each vector is 4 bytes with the following format:

Raising Exceptions

When an exception is raised, the following process takes place:

Since PC is incremented for each byte of instruction code fetched from memory, the value of PC that gets pushed to the stack will be the offset of the first byte of the instruction that follows either the instruction that raised the exception or the instruction that was executing when the interrupt was requested.

Editor's Note: On V Series CPUs that have an MD flag in PSW, it is set when an exception is raised.

Returning from Exceptions

When all of the processing for an exception has completed, the program can return to the main code with the RETI instruction. This instruction performs the following operations:

If an interrupt is not acknowledged before returning from an instruction, the interrupt request will remain active and the CPU will immediately raise another exception for it.

Editor's Note: Research is needed to determine whether all IRQ lines remain in effect if an interrupt is not acknowledged. The WonderWitch documentation explicitly identifies some interrupts as being edge-driven and others level-driven, but given interrupt requests need to be held during instruction execution, it's not clear exactly how the IRQ state reflects what the hardware is doing.

List of Exceptions

The following exceptions result from CPU operations (software interrupts) and have fixed vectors:

Any exception raised by the CPU in the list above will be processed before any interrupt requests in the list below.

The following exceptions are interrupts raised by components other than the CPU. Their vectors are not fixed: their number is added to the base vector specified by INT_BASE (see below):

^[note] Editor's Note: These interrupts need research.

A "level" interrupt will constantly issue its request until acknowledged. Returning from the handler routine without acknowledging the request will immediately cause the handler to run again.

An "edge" interrupt will only issue its request once as a pulse. Returning from the handler routine without acknolweding the request will not cause the handler to run again, but no further interrupts with the same vector can be requested until the previous one is acknowledged.

In the event two or more interrupts are requested simultaneously, the one with the greatest vector will be processed first.

Hardware interrupts cause pending HALT instructions to complete, even if interrupts are otherwise masked by the IE flag in PSW.

Editor's Note: Research is needed to verify the mechanics of "level" and "edge".

Managing Interrupts

Hardware interrupts do not have fixed vectors. Instead, their effective vector is calculated by taking a global base vector and adding to it the interrupt's vector number as shown in the list above.

The base interrupt vector is configured through the following I/O port:

This port is ostensibly an unsigned 8-bit value directly representing the hardware interrupt base vector number. However, the lowest 3 bits are ignored (limiting the base vector to multiples of 8) and are undefined when read.

Interrupt requests are managed through the following I/O ports, all of which have the same format:

Each bit in these ports corresponds to one of the hardware interrupts, with the position of each bit matching the interrupt's relative vector index.

The bits in INT_ENABLE specify which hardware interrupt situations are permitted. INT_ENABLE can be both read and written.

When an interrupt situation occurs while the corresponding bit is set in INT_ENABLE, the corresponding bit in INT_CAUSE becomes set. While INT_CAUSE is non-zero, a CPU interrupt will be requested (the processing of which can be masked by the IE flag in PSW). Clearing bits in INT_ENABLE has no effect on INT_CAUSE. INT_CAUSE is read-only and writes have no effect.

When a 1 is written to a bit in INT_CAUSE_CLEAR, the corresponding interrupt is acknowledged and the corresponding bit in INT_CAUSE is cleared, causing any active request for that interrupt to be canceled. When a 0 is written to a bit in INT_CAUSE_CLEAR, no action is taken for that interrupt. INT_CAUSE_CLEAR is write-only and its contents are undefined when read.

NMI - Non-Maskable Interrupt

The non-maskable interrupt (NMI) is a hardware interrupt that cannot be ignored by the CPU: it will invoke its handler routine regardless of the state of the IE flag in PSW, even if another interrupt is already being handled. The NMI is automatically acknowledged as soon as it is triggered, before its handler routine is invoked.

The NMI is configured through the following I/O port:

When the system battery gets low on voltage, a dedicated LCD segment activates. If BAT is set when this occurs, an NMI will be triggered. If BAT becomes set while the battery voltage is already low, an NMI will be triggered immediately. While the battery voltage is low, BAT must be cleared then set again in order to trigger another NMI.

Memory and Register

Instructions

CVTBW - Convert Byte to Word

Sign-extends AL into AW. If the highest bit of AL is clear, stores 0x00 into AH. Otherwise, stores 0xFF into AH.

CVTWL - Convert Word to Long

Sign-extends AW into DW,AW. If the highest bit of AW is clear, stores 0x0000 into DW. Otherwise, stores 0xFFFF into DW.

IN - Input

Inputs the value from the I/O port pointed to by src and stores it into AL. If 16-bit, inputs the value from the I/O port pointed to by src + 1 and stores it into AH.

The Accumulator/Immediate variant of this instruction provides the lower 8 bits of an I/O port as one additional byte of program code. The upper 8 bits of the port are zero.

LDEA - Load Effective Address

Calculates the offset of a memory operand and stores the result into a 16-bit register.

If the memory operand specifies a register, the value in that register is stored to the destination as though the instruction were MOV.

If the memory operand specifies an offset, the value at that offset is not read from memory. Instead, the offset itself is stored to the destination.

MOV - Move

Takes the value from src and stores it into dest.

After executing the Memory/Segment Register variant of this instruction and prior to executing the following instruction, interrupts will not be accepted and the break flag (BRK) will not function.

When transferring between AH and PSW, only the lower 8 bits of PSW are relevant.

The Accumulator/Direct Memory variant of this instruction provides a 16-bit memory offset as two additional bytes of program code (low byte first). The memory at this offset is accessed by the operation.

The three-operand variants of this instruction load 32 bits from the memory pointed to by the memory operand. The lower 16 bits (low byte first) are stored into the 16-bit register operand and the upper 16 bits (low byte first) are stored into the segment register operand.

If a three-operand variant of this instruction specifies a register for the memory operand, the offset accessed in memory will be undefined.

The number of cycles taken by the Memory/Segment Register variant of this instruction depends on the memory operand:

OUT - Output

Outputs the value of AL to the I/O port pointed to by dest. If 16-bit, outputs the value of AH to the I/O port pointed to by dest + 1.

The Immediate/Accumulator variant of this instruction provides the lower 8 bits of an I/O port as one additional byte of program code. The upper 8 bits of the port are zero.

POP - Pop

Retrieves a 16-bit value from the stack and stores it in the operand. During a pop operation, the value is loaded from the memory pointed to by SS:SP (low byte first), then SP is incremented by 2.

After executing the Segment Register variant of this instruction and prior to executing the following instruction, interrupts will not be accepted and the break flag (BRK) will not function.

The Register and Memory variants of this instruction are 16-bit operations.

The R variant of this instruction performs the following algorithm:

Status flags in PSW will only be modified when PSW is the operand. If the PSW variant of this instruction causes the interrupt enable flag (IE) to transition from clear to set, then prior to executing the following instruction, interrupts will not be accepted, but the break flag (BRK) will continue to function.

The number of cycles taken by the Memory variant of this instruction depends on the operand:

Editor's Note: The instruction set documentation indicates anomalous behavior when using PUSH SP followed by POP SP. This needs to be investigated.

PUSH - Push

Stores a 16-bit value on the stack. During a push operation, SP is decremented by 2, then the value is stored into memory at the offset pointed to by SP (low byte first).

All push operations are 16-bit. This affects which data is accessed by the Register and Memory variants of this instruction, and the size of the immediate operand.

The R variant of this instruction performs the following algorithm:

The Memory variant of this instruction is a 16-bit operation.

The number of cycles taken by the Memory variant of this instruction depends on the operand:

SALC - Set AL on Carry

Sets AL according to the status of CY. If CY is clear, stores 0x00 into AL. Otherwise, stores 0xFF into AL.

Editor's Note: This instruction is historically undocumented, even by Intel. It was first documented in the instruction set for the Pentium Pro (P6/i686) in 1995, but has been confirmed to be present in all of Intel's x86 CPUs all the way back to the 8086. Its purpose is to assist compilers by succinctly transferring boolean results into AL (for use as function return values) without affecting any of the status flags, and it is provided by V30MZ for compatibility reasons.

TRANS - Translate

Calculates a memory offset as the unsigned sum of BW and AL, and loads the byte at that offset into AL.

This instruction's operands are implicit and may be written in other ways:

The default segment register for this instruction is DS0. The segment register to use can be selected with a segment override prefix.

XCH - Exchange

Exchanges the values stored in the operands.

The Accumulator/Register variant of this instruction is a 16-bit operation.

This instruction may be written with its operands reversed, as the operation will be unchanged.

When the Accumulator/Register variant of this instruction is used to exchange AW with itself, it is regarded as its own instruction:

The number of cycles taken by the Register/Memory variant of this instruction depends on the memory operand:

Arithmetic

Instructions

ADD - Add

Adds the two operands. The result is stored in the left operand.

The zero flag (Z) is set when the result of the addition is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the operands have the same sign and the result has the opposite sign, or is cleared otherwise.

The carry flag (CY) is set when the unsigned sum exceeds 0xFF for byte or 0xFFFF for word, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set when the unsigned sum of the lowest 4 bits of the operands exceeds 0xF, or is cleared otherwise.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

ADDC - Add with Carry

Adds the two operands, plus 1 more if the carry flag (CY) was set. The result is stored in the left operand.

The zero flag (Z) is set when the result of the addition is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the operands have the same sign and the result has the opposite sign, or is cleared otherwise.

The carry flag (CY) is set when the unsigned sum exceeds 0xFF for byte or 0xFFFF for word, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set when the unsigned sum of the lowest 4 bits of the operands exceeds 0xF, or is cleared otherwise.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

ADJ4A - Adjust Nibble Add

When ADD or ADDC is used on two-digit binary-coded decimal numbers, ADJ4A can be used to adjust the result in the AL register in order to produce the correct two-digit binary-coded decimal result.

The adjustment performs the following algorithm:

If the operands of the original addition were not two-digit binary-coded decimal, the result of the adjustment will be nonsense.

The zero flag (Z) is set when the result of the adjustment is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the adjustment is set, or is cleared otherwise.

The overflow flag (V) has an unspecified state after this instruction completes.

The carry (CY) and auxiliary carry (AC) flags are updated according to the above algorithm.

The parity flag (P) is set when the number of set bits in the result is even, or is cleared otherwise.

ADJ4S - Adjust Nibble Subtract

When SUB or SUBC is used on two-digit binary-coded decimal numbers, ADJ4S can be used to adjust the result in the AL register in order to produce the correct two-digit binary-coded decimal result.

The adjustment performs the following algorithm:

If the operands of the original subtraction were not two-digit binary-coded decimal, the result of the adjustment will be nonsense.

The zero flag (Z) is set when the result of the adjustment is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the adjustment is set, or is cleared otherwise.

The overflow flag (V) has an unspecified state after this instruction completes.

The carry (CY) and auxiliary carry (AC) flags are updated according to the above algorithm.

The parity flag (P) is set when the number of set bits in the result is even, or is cleared otherwise.

ADJBA - Adjust Byte Add

When ADD or ADDC is used on one-digit binary-coded decimal numbers, ADJBA can be used to adjust the values in the AL and AH registers in order to produce the correct two-digit binary-coded decimal result.

The adjustment performs the following algorithm:

If the operands of the original addition were not one-digit binary-coded decimal, the result of the adjustment will be nonsense.

The zero (Z), sign (S), carry (CY) and auxiliary carry (AC) flags are updated according to the above algorithm.

The overflow (V) flag is always cleared.

The parity (P) flag is always set.

★ In the V Series specification, the zero (Z), sign (S), overflow (V) and parity (P) flags have unspecified states after this instruction completes.

ADJBS - Adjust Byte Subtract

When SUB or SUBC is used on one-digit binary-coded decimal numbers, ADJBS can be used to adjust the result in the AL and AH registers in order to produce the correct two-digit binary-coded decimal output.

The adjustment performs the following algorithm:

If the operands of the original subtraction were not 4-bit binary-coded decimal, the result of the adjustment will be nonsense.

The zero (Z), sign (S), carry (CY) and auxiliary carry (AC) flags are updated according to the above algorithm.

The overflow (V) flag is always cleared.

The parity (P) flag is always set.

★ In the V Series specification, the zero (Z), sign (S), overflow (V) and parity (P) flags have unspecified states after this instruction completes.

CMP - Compare

Subtracts the operands, updating the status flags in the process, and discards the result.

The zero flag (Z) is set when the result of the subtraction is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the operands have opposite signs and the left operand and result have opposite signs, or is cleared otherwise.

The carry flag (CY) is set when the unsigned difference passes zero, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set when the unsigned difference of the lowest 4 bits of the operands passes zero, or is cleared otherwise.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

CVTBD - Convert Binary to Decimal

An 8-bit, unsigned division is performed as AL / src, the quotient is stored into AH, and the remainder is stored into AL.

If the divisor is zero, an exception is raised with vector 0. The value of AW is undefined in this situation.

The zero flag (Z) is set when the resulting value of AL is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the resulting value of AL is set, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the resulting value of AL is even, or is cleared otherwise.

The overflow (V), carry (CY) and auxiliary carry (AC) flags have unspecified states after this instruction completes.

Editor's Note: The intended use of this instruction is to use an operand of 10 to adjust the result of two multiplied binary-coded decimal values after using MULU.

Editor's Note: Formally, the V Series specification does not include an operand for this instruction, but provides a second byte 0x0A as a sort of 16-bit opcode. The V30MZ treats this byte as an operand in accordance with the 8086 family specification.

CVTDB - Convert Decimal to Binary

An 8-bit, unsigned multiplication is performed as AH * src, the value in AL is added, the lower 8 bits of the result are stored into AL, and zero is stored into AH.

V30MZ processes this instruction by performing MULU followed by ADD. All flags—including overflow (V), carry (CY) and auxiliary carry (AC)—are updated according to the usual operations of ADD.

★ In the V Series specification, the overflow (V), carry (CY) and auxiliary carry (AC) flags have unspecified states after this instruction completes.

Editor's Note: The intended use of this instruction is to use an operand of 10 to prepare a binary-coded decimal value to be subsequently divided using DIVU, such that it will produce the correct binary-coded decimal result.

Editor's Note: Formally, the V Series specification does not include an operand for this instruction, but provides a second byte 0x0A as a sort of 16-bit opcode. The V30MZ treats this byte as an operand in accordance with the 8086 family specification.

DEC - Decrement

Subtracts 1 from the operand and stores the result back into the operand.

The Register variant of this instruction is a 16-bit operation.

The zero flag (Z) is set when the result of the subtraction is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the original value was -128 for byte or -32,768 for word, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set if the lowest 4 bits of the original value were all clear, or is cleared otherwise.

The number of cycles taken by the Memory variant of this instruction depends on the operand:

DIV - Divide Signed

As an 8-bit operation, a signed division is performed as AW / mem, the remainder is stored into AH and the quotient is stored into AL.

As a 16-bit operation, a 32-bit value is produced with DW as the upper bits and AW as the lower bits, a signed division is performed as this value / mem, the remainder is stored into DW and the quotient is stored into AW.

The quotient is truncated to an integer (towards zero), and the remainder has the same sign as the dividend.

If the divisor is zero or the magnitude of the quotient (after truncation) exceeds ±0x7F for 8-bit or ±0x7FFF for 16-bit, an exception is raised with vector 0. The values of AW and DW (if 16-bit) are undefined in this situation.

The zero (Z), sign (S), overflow, (V), carry (CY), parity (P) and auxiliary carry (AC) flags have unspecified states after this instruction completes.

The number of cycles taken by this instruction depends on the operation size and operand:

Editor's Note: Most x86 CPUs after the Intel 8089 include the maximum negative value (-128 and -32,768) in the range of valid quotients. The V Series specification matches the range defined in the original 8086 family specification, which excludes the maximum negative value.

Editor's Note: Although the values in DW (if 16-bit) and AW are formally undefined in the event of an exception, hardware testing suggests that these registers are simply not modified.

DIVU - Divide Unsigned

As an 8-bit operation, an unsigned division is performed as AW / mem, the remainder is stored into AH and the quotient is stored into AL.

As a 16-bit operation, a 32-bit value is produced with DW as the upper bits and AW as the lower bits, an unsigned division is performed as this value / mem, the remainder is stored into DW and the quotient is stored into AW.

The quotient is truncated to an integer (towards zero).

If the divisor is zero or the quotient (after truncation) exceeds 0xFF for 8-bit or 0xFFFF for 16-bit, an exception is raised with vector 0. The values of AW and DW (if 16-bit) are undefined in this situation.

The zero (Z), sign (S), overflow, (V), carry (CY), parity (P) and auxiliary carry (AC) flags have unspecified states after this instruction completes.

The number of cycles taken by this instruction depends on the operation size and operand:

Editor's Note: Although the values in DW (if 16-bit) and AW are formally undefined in the event of an exception, hardware testing suggests that these registers are simply not modified.

FPO1 - Floating Point Operation 1

Performs no operation.

Although this instruction performs no operation, additional bytes of instruction code may still be present depending on the memory operand. If the memory operand specifies an offset, no memory is actually accessed.

Editor's Note: This instruction was carried over from the base V Series instruction set. Its original function was to control a floating-point coprocessor, but the coprocessor feature is not supported on V30MZ.

INC - Increment

Adds 1 to the operand and stores the result back into the operand.

The Register variant of this instruction is a 16-bit operation.

The zero flag (Z) is set when the result of the addition is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the original value was 127 for byte or 32,767 for word, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) will be set if the lowest 4 bits of the original value were all set, or is cleared otherwise.

The number of cycles taken by the Memory variant of this instruction depends on the operand:

MUL - Multiply Signed

Performs a signed multiplication of the operands. The exact operation depends on which variant of the instruction is being executed.

The three-operand variant of this instruction performs a signed 16-bit multiplication. The memory and immediate operands are multiplied together, and the lower 16 bits of the product are stored into the register operand.

If the three-operand variant of this instruction specifies a memory operand that matches the register operand, the register can optionally be written only once, forming a two-operand instruction with it and the immediate operand.

The Memory variant of this instruction performs a signed 8- or 16-bit multiplication with the accumulator and the operand. As an 8-bit operation, the upper 8 bits of the product are stored into AH and the lower 8 bits of the result are stored into AL. As a 16-bit operation, the upper 16 bits of the result are stored into DW and the lower 16 bits of the result are stored into AW.

The overflow (V) and carry (CY) flags are set if the full product is not a sign-extension of the lowest 8 or 16 bits of the product (depending on the size of the operation), or are cleared otherwise.

The zero (Z) flag is always set.

The sign (S), parity (P) and auxiliary carry (AC) flags are always cleared.

The number of cycles taken by either variant of this instruction depends on the memory operand:

★ In the V Series specification, the zero (Z), sign (S), parity (P) and auxiliary carry (AC) flags have unspecified states after this instruction completes.

MULU - Multiply Unsigned

Performs an unsigned multiplication of the accumulator and the operand. As an 8-bit operation, the upper 8 bits of the product are stored into AH and the lower 8 bits of the product are stored into AL. As a 16-bit operation, the upper 16 bits of the result are stored into DW and the lower 16 bits of the result are stored into AW.

The overflow (V) and carry (CY) flags will be set if the upper half of the product is not zero, or are cleared otherwise.

The zero (Z) flag is always set.

The sign (S), parity (P) and auxiliary carry (AC) flags are always cleared.

The number of cycles taken by this instruction depends on the operand:

★ In the V Series specification, the zero (Z), sign (S), parity (P) and auxiliary carry (AC) flags have unspecified states after this instruction completes.

NEG - Negate

Calculates the additive inverse of dest by subtracting dest from zero, and stores the result back into dest.

The zero flag (Z) is set when the result of the negation is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set if the original value was -128 for byte or -32,768 for word, or is cleared otherwise.

The carry flag (CY) is set if the original value was not zero, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set if any of the lowest 4 bits of the original value were set, or is cleared otherwise.

The number of cycles taken by this instruction depends on the operand:

SUB - Subtract

Subtracts the two operands. The result is stored in the left operand.

The zero flag (Z) is set when the result of the subtraction is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the operands have opposite signs and the left operand and result have opposite signs, or is cleared otherwise.

The carry flag (CY) is set when the unsigned difference passes zero, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set when the unsigned difference of the lowest 4 bits of the operands passes zero, or is cleared otherwise.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

SUBC - Subtract with Carry

Subtracts the two operands, minus 1 more if the carry flag (CY) was set. The result is stored in the left operand.

The zero flag (Z) is set when the result of the subtraction is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow flag (V) is set when the operands have opposite signs and the left operand and result have opposite signs, or is cleared otherwise.

The carry flag (CY) is set when the unsigned difference passes zero, or is cleared otherwise.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) is set when the unsigned difference of the lowest 4 bits of the operands passes zero, or is cleared otherwise.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

Bitwise

Instructions

AND - And

Computes the bitwise AND of the operands. The result is stored in the left operand.

The zero flag (Z) is set when the result of the operation is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow (V) and carry (CY) flags are cleared.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

NOT - Not

Inverts the bits of the operand.

The number of cycles taken by this instruction depends on the operand:

OR - Or

Computes the bitwise OR of the operands. The result is stored in the left operand.

The zero flag (Z) is set when the result of the operation is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow (V) and carry (CY) flags are cleared.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

ROL - Rotate Left

Performs a left bitwise rotation on the value of the destination by the number of bits given by the source, and stores the result into the destination.

For each bit of rotation, a left shift is performed on dest, and the previous highest bit becomes the new lowest bit.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

If src is zero, the carry flag (CY) is not modified. Otherwise, it becomes a copy of the lowest bit of the result of the operation.

The overflow flag (V) is set if the highest bit of dest changes during the final bit of rotation, or is cleared otherwise.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

★ In the V Series specification, the overflow (V) flag has unspecified state after the Memory/Immediate and Memory/CL variants of this instruction complete.

ROLC - Rotate Left with Carry

Performs a left bitwise rotation on a value formed by treating CY as an additional bit one place higher than the highest bit of the destination. The number of bits to rotate is given by the source, and the result is stored into CY and the destination.

For each bit of rotation, a left shift is performed on dest, CY is used as the new lowest bit of dest, and the previous highest bit of dest becomes the new CY.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

If src is zero, the carry flag (CY) is not modified. Otherwise, it is modified as described above.

The overflow flag (V) is set if the highest bit of dest changes during the final bit of rotation, or is cleared otherwise.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

★ In the V Series specification, the overflow (V) flag has unspecified state after the Memory/Immediate and Memory/CL variants of this instruction complete.

ROR - Rotate Right

Performs a right bitwise rotation on the value of the destination by the number of bits given by the source, and stores the result into the destination.

For each bit of rotation, a right shift is performed on dest, and the previous lowest bit becomes the new highest bit.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

If src is zero, the carry flag (CY) is not modified. Otherwise, it becomes a copy of the highest bit of the result of the operation.

The overflow flag (V) is set if the highest bit of dest changes during the final bit of rotation, or is cleared otherwise.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

★ In the V Series specification, the overflow (V) flag has unspecified state after the Memory/Immediate and Memory/CL variants of this instruction complete.

RORC - Rotate Right with Carry

Performs a right bitwise rotation on a value formed by treating CY as an additional bit one place higher than the highest bit of the destination. The number of bits to rotate is given by the source, and the result is stored into CY and the destination.

For each bit of rotation, a right shift is performed on dest, CY is used as the new highest bit of dest, and the previous lowest bit of dest becomes the new CY.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

If src is zero, the carry flag (CY) is not modified. Otherwise, it is modified as described above.

The overflow flag (V) is set if the highest bit of dest changes during the final bit of rotation, or is cleared otherwise.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

★ In the V Series specification, the overflow (V) flag has unspecified state after the Memory/Immediate and Memory/CL variants of this instruction complete.

SHL - Shift Left

Performs a left bitwise shift on the value of the destination by the number of bits given by the source, and stores the result into the destination. Bits shifted in on the right are zeroes.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

The zero flag (Z) is set when the result of the shift is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

If src is zero, the carry flag (CY) is not modified. Otherwise, it becomes a copy of the last bit that was shifted out of the left side of the register.

For the Memory/1 variant of this instruction, the overflow flag (V) is set if the highest bit of dest changes, or is cleared otherwise. For other variants of this instruction, the overflow flag has an unspecified state after the instruction completes.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

SHR - Shift Right

Performs a right bitwise shift on the value of the destination by the number of bits given by the source, and stores the result into the destination. Bits shifted in on the left are zeroes.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

The zero flag (Z) is set when the result of the shift is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

If src is zero, the carry flag (CY) is not modified. Otherwise, it becomes a copy of the last bit that was shifted out of the right side of the register.

For the Memory/1 variant of this instruction, the overflow flag (V) is set if the highest bit of dest changes, or is cleared otherwise. For other variants of this instruction, the overflow flag has an unspecified state after the instruction completes.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

SHRA - Shift Right Arithmetic

Performs a right bitwise shift on the value of the destination by the number of bits given by the source, and stores the result into the destination. Bits shifted in on the left are copies of the highest bit of the original value.

Only the lowest 5 bits of src are used in the operation.

If dest is an offset, the read and write memory accesses are performed even when src is zero.

The size of the immediate operand in the Memory/Immediate variant of this instruction is always one byte.

The zero flag (Z) is set when the result of the shift is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

If src is zero, the carry flag (CY) is not modified. Otherwise, becomes a copy of the last bit that was shifted out of the right side of the register.

For the Memory/1 variant of this instruction, the overflow flag (V) is set if the highest bit of dest changes, or is cleared otherwise. For other variants of this instruction, the overflow flag has an unspecified state after the instruction completes.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The numbers of cycles taken by the Memory/Immediate and Memory/CL variants of this instruction depend on the memory operand:

The number of cycles taken by the Memory/1 variant of this instruction depends on the memory operand:

TEST - Test

Computes the bitwise AND of the operands, updates the status flags accordingly, and discards the result.

The zero flag (Z) is set when the result of the operation is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow (V) and carry (CY) flags are cleared.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The numbers of cycles taken by the Register/Memory and Memory/Immediate variants of this instruction depend on the memory operand:

XOR - Exclusive Or

Computes the bitwise exclusive OR of the operands. The result is stored in the left operand.

The zero flag (Z) is set when the result of the operation is zero, or is cleared otherwise.

The sign flag (S) is set when the highest bit of the result is set, or is cleared otherwise.

The overflow (V) and carry (CY) flags are cleared.

The parity flag (P) is set when the number of set bits in the lower 8 bits of the result is even, or is cleared otherwise.

The auxiliary carry flag (AC) has an unspecified state after this instruction completes.

The number of cycles taken by the Memory/Register variant of this instruction depends on the operands:

The number of cycles taken by the Memory/Immediate variant of this instruction depends on the operands:

CPU Control

Prefixes

Instructions

BUSLOCK - Bus Lock Prefix

This is a prefix that applies to all instructions.

When the instruction prefixed by BUSLOCK executes, the CPU has full control of the memory bus until the instruction completes. Any other component that attempts to access the bus during this time will be stalled, and any interrupts will be held, until the lock is released.

If the prefixed instruction is a block instruction that is also prefixed by REP, the bus will remain locked until all repetitions are fully processed.

BR - Branch

Unconditionally redirects the program to another address: